Drimva

Arm

Senior Security IP Design Engineer

$162K–$218K

Austin, Texas +2 · Senior · Full-time · Posted Aug 6, 2026

Location
Austin, Texas
San Diego, California
Chandler, Arizona
Experience
No specific number of years stated; asks for a successful track record of sophisticated ownership and leadership in designing and productizing Compute, Multimedia, or Security Sub-Systems and SoCs.
Education
Bachelor's or Graduate degree in Computer Science or Electrical/Computer Engineering; no equivalent-experience alternative stated.

About the job

Design, verify, and productize hardware security IP and subsystems for SoCs, from architecture and RTL through sign-off.

What you'll do

  • Develop security hardware architectures, specifications, RTL, and constraints; lead design exploration, optimization, and structural checks.
  • Partner with verification and implementation teams on test plans, verification closure, debugging, and functional, power, and performance sign-off.
  • Contribute to team methodologies and mentor colleagues while coordinating project plans, roadmaps, initiatives, and schedules.

What they ask for

  • Advanced understanding of hardware Verilog RTL design, verification, and EDA methodologies.
  • Proven experience in security hardware and related areas including embedded processor systems, applied cryptography, secure boot, key management, and access controls.
  • Proven SoC architecture experience, including multi-clock and multi-power domains, AXI/AHB protocols, and reset architectures.
  • Competency in synthesis, timing analysis, constraint development, and ECO methodologies.

Nice to have

  • Familiarity with ARM-based designs and/or ARM System Architectures.
  • Experience with SystemVerilog and verification methodologies such as UVM/OVM, Portable Stimulus, or hardware/firmware co-verification.

Pay

$161,500-$218,500 per year (base salary)

Tools

Verilog RTL, AXI/AHB, CDC, RDC, UPF, Perl, Python, TCL

AI focus

No AI-related job duties stated. Applicants may use AI for preparation but not to complete assigned assessment tasks; AI-supported or assistive technology for reasonable adjustments is addressed separately.

Model-written summary · the original posting is authoritative

First seen Oct 28, 2026 · Last verified Nov 5, 2026 (UTC)