Arm
Staff DFT Engineer
$198K–$268K
Austin, Texas · Staff · Full-time · Posted Aug 24, 2026
- Experience
- 10+ years in Design for Test.
- Education
- Bachelor’s or Master’s degree in Electronic Engineering, Computer Engineering, or a related field.
About the job
Architects, implements, and validates design-for-test (DFT) for SoCs and subsystems through silicon test and characterization.
What you'll do
- Insert and validate DFT logic, run simulations, generate ATPG patterns, and resolve coverage issues.
- Develop DFT timing requirements, review timing reports, and support timing closure across design and implementation teams.
- Support ATE testing, silicon debug, characterization, and validation with test and product engineering teams.
What they ask for
- Bachelor’s or Master’s degree in Electronic Engineering, Computer Engineering, or a related field.
- 10+ years of experience in Design for Test.
- Core DFT experience in areas such as scan insertion/compression, MBIST, LBIST, JTAG/IJTAG, ATPG, fault simulation, or silicon debug.
- Experience coding Verilog RTL, TCL and/or Perl, and with Cadence and/or Synopsys DFT and simulation tools.
Nice to have
- Familiarity with SoC architectures, multi-clock domains, low-power build practices, or Arm IP.
- Experience with high-performance implementation and DFT timing constraints, datacenter chips, or 2.5D/3D test.
Pay
$198,100-$268,000 per year (base salary)
Tools
Siemens DFT tools, Streaming Scan Network (SSN), Verilog RTL, TCL, Perl, Cadence, Synopsys, ATE
Model-written summary · the original posting is authoritative