Arm
Staff Signal Integrity Engineer
$209K–$283K
San Jose, California +1 · Staff · Full-time · Posted Oct 28, 2026
- Location
- San Jose, California
Chandler, Arizona - Experience
- 8+ years in high-speed signal integrity engineering, semiconductor packaging, or system-level electrical design.
- Education
- BS/MS/Ph.D. in Electrical Engineering or a related field.
About the job
Leads signal-integrity design, simulation, optimization, and validation for high-speed interconnects in AI Superchip and data center platforms.
What you'll do
- Drive SI design, modeling, simulation, and validation across SoC, advanced packaging, PCB, and system-level interconnects.
- Analyze and optimize high-speed channels for memory, PCIe/CXL, Ethernet, die-to-die, and SerDes interfaces; develop and validate electrical models.
- Lead SI optimization and collaborate across teams on design guidelines, simulation-to-silicon correlation, and electrical sign-off.
What they ask for
- BS/MS/Ph.D. in Electrical Engineering or a related field.
- Strong expertise with SI simulation and 3D electromagnetic modeling tools such as Ansys HFSS, SIwave, Keysight ADS, or equivalent.
- Solid understanding of high-speed I/O signaling, transmission lines, S-parameters, crosstalk, equalization, and timing/BER analysis.
- Experience with advanced packaging, DDR/LPDDR memory interfaces, PCIe/CXL, and high-speed SerDes technologies.
Nice to have
- Experience with AI/HPC supercomputing platforms, advanced chiplet integration, package-to-board co-design, silicon bring-up, and simulation-to-measurement correlation.
Pay
$209,100-$282,900 per year (USD, base salary)
Tools
Ansys HFSS, SIwave, Keysight ADS, DDR5/LPDDR, PCIe/CXL, Ethernet, SerDes, IBIS/IBIS-AMI
Model-written summary · the original posting is authoritative