Astera Labs
Advanced DV Engineer Intern
San Jose, CA +1 · Internship · Posted Sep 8, 2026
- Location
- San Jose, CA
California - Experience
- No specific number of years stated.
- Education
- Enrollment in a bachelor’s, master’s, or Ph.D. program in electrical engineering, computer engineering, computer science, or a related field.
About the job
Validates ASIC and system designs before silicon by developing verification tests and infrastructure, analyzing coverage, debugging failures, and supporting simulation and formal verification.
What you'll do
- Translate design requirements into test plans, scenarios, checkers, and coverage goals; develop and maintain SystemVerilog and UVM testbench components.
- Run and debug simulations and regressions, analyze coverage, and identify verification gaps or root causes.
- Support formal verification and improve automation; document and present project results while collaborating across engineering teams.
What they ask for
- Enrollment in a bachelor’s, master’s, or Ph.D. program in electrical engineering, computer engineering, computer science, or a related field.
- Coursework, research, or project experience in digital logic, computer architecture, ASIC/FPGA design, verification, embedded systems, or hardware/software integration.
- Programming or verification experience with SystemVerilog, Verilog, C, C++, Python, or a comparable language.
- Familiarity with digital design, simulation, debugging, Linux, Git, command-line tools, and technical documentation.
Nice to have
- Experience with UVM, SystemVerilog Assertions, constrained-random testing, or coverage-driven verification.
- Exposure to protocols such as PCIe, CXL, or AXI, or simulation and formal tools such as Verdi, DVE, VCS, Questa, Xcelium, or VC Formal.
Pay
$35/hour to $55/hour (hourly rate); $500-per-week (housing/relocation stipend)
Tools
SystemVerilog, UVM, Verilog, C, C++, Python, Tcl, Linux
Model-written summary · the original posting is authoritative