AMS Design Verification Engineer Intern

What you'll do

• Develop and execute simulation-based test plans, test cases, and verification components for digital ASIC blocks and subsystems.
• Debug simulation failures, analyze results, and assist with regression testing and verification improvements.
• Document verification progress and collaborate with RTL design, architecture, and verification engineers.

What they ask for

• Currently pursuing a Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field.
• Fundamental understanding of digital logic and basic hardware design concepts, including clocks, resets, registers, and state machines.
• Basic programming knowledge in at least one language such as C, C++, Python, or SystemVerilog.
• Familiarity with digital simulation or hardware design through coursework, academic projects, research, or internships; ability and willingness to work onsite in San Jose, California.

Nice to have

• Experience or exposure to Verilog/SystemVerilog, RTL simulation, waveform debugging, verification concepts, or functional coverage.
• Exposure to UVM or constrained-random methodologies; scripting experience; or familiarity with ASIC/FPGA flows and high-speed interfaces.

Pay

$35/hour to $55/hour (hourly pay); $500-per-week (housing/relocation stipend)

Tools

SystemVerilog, UVM, Python, Tcl, Shell, C, C++, Perl