Astera Labs
AMS Digital Design Engineer Intern
San Jose, CA +1 · Internship · Posted Oct 13, 2026
- Location
- San Jose, CA
California - Experience
- No prior industry experience is required; relevant coursework, academic projects, research, and internships will be considered.
- Education
- Currently pursuing a Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field.
About the job
Develop and debug synthesizable RTL for digital ASIC blocks, collaborating with cross-functional teams through design, verification, and implementation activities.
What you'll do
- Develop, integrate, and debug Verilog/SystemVerilog RTL for ASIC blocks and subsystems.
- Run RTL simulations, support functional debugging and design-quality checks, and work with verification engineers.
- Gain exposure to ASIC synthesis, timing analysis, physical design, and cross-functional integration.
What they ask for
- Currently pursuing a Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field.
- Fundamental understanding of digital logic design and basic knowledge of Verilog or SystemVerilog.
- Familiarity with digital design concepts such as clocks, resets, counters, FIFOs, and register-based interfaces.
- Ability and willingness to work onsite in San Jose, California.
Nice to have
- Experience developing Verilog/SystemVerilog RTL through projects, FPGA development, research, or internships.
- Familiarity with RTL simulation tools, ASIC/FPGA design flows, or scripting languages.
Pay
$35/hour to $55/hour (hourly rate); $500-per-week (housing/relocation stipend)
Tools
Verilog, SystemVerilog, Python, Tcl, Perl, Shell, PCI Express, Ethernet
AI focus
AI and cloud computing are listed as areas of interest; no specific AI development work is described.
Model-written summary · the original posting is authoritative