Astera Labs
AMS Digital Design Engineer NCG
$150K–$170K
San Jose, CA +1 · Full-time · Posted Oct 13, 2026
- Location
- San Jose, CA
California - Education
- Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, completed or expected by the start date.
About the job
Develops synthesizable RTL for digital ASIC blocks and subsystems, debugs functionality, and supports integration and implementation across the ASIC development flow.
What you'll do
- Design, implement, integrate, and debug Verilog/SystemVerilog RTL for digital ASIC blocks.
- Run RTL simulations, resolve functional issues, and support lint and other design-quality checks.
- Collaborate across engineering teams on synthesis, timing analysis, physical-design handoff, and design readiness.
What they ask for
- Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, completed or expected by the start date.
- Strong foundation in digital logic design, including combinational and sequential logic, flip-flops, finite state machines, and basic datapaths.
- Experience with Verilog or SystemVerilog through coursework, academic projects, research, FPGA development, or internships.
- Ability and willingness to work onsite in San Jose, California.
Nice to have
- Experience with RTL simulation and waveform-debugging tools or exposure to digital ASIC or FPGA design flows.
- Experience with scripting languages such as Python, Tcl, Perl, or Shell; exposure to high-speed interfaces or verification concepts.
Pay
$150,000 - $170,0000 USD base salary
Tools
Verilog, SystemVerilog, Python, Tcl, Perl, Shell, UVM, PCI Express
Model-written summary · the original posting is authoritative