Astera Labs
Design Architecture Engineer Intern
San Jose, CA +1 · Internship · Posted Sep 8, 2026
- Location
- San Jose, CA
California - Experience
- No number of years specified.
- Education
- Enrollment in a bachelor’s, master’s, or Ph.D. program in electrical engineering, computer engineering, computer science, or a related field.
About the job
Defines ASIC and system architecture and microarchitecture, evaluates design tradeoffs, and produces specifications and recommendations to guide implementation and verification.
What you'll do
- Develop architectural and microarchitectural specifications for blocks, interfaces, and system behavior.
- Model performance, capacity, traffic, or resources and analyze design tradeoffs.
- Coordinate specification handoffs across engineering teams and present a scoped architecture project.
What they ask for
- Enrolled in a bachelor’s, master’s, or Ph.D. program in electrical engineering, computer engineering, computer science, or a related field.
- Coursework, research, or project experience in a relevant area such as computer architecture, digital systems, ASIC/FPGA design, embedded systems, high-speed interfaces, or hardware/software integration.
- Understanding of digital design concepts, including datapaths, state machines, registers, memory systems, interrupts, clocks, resets, and interfaces.
- Programming, scripting, or modeling experience with Python, C, C++, SystemVerilog, spreadsheets, or a comparable toolset.
Nice to have
- Experience writing architecture, microarchitecture, design, interface, protocol, or software-programming specifications.
- Familiarity with high-speed interconnect architectures or experience with performance modeling and bandwidth/latency analysis.
Pay
$35/hour to $55/hour (hourly rate; base salary not stated); $500-per-week (housing/relocation stipend)
Tools
Python, C, C++, SystemVerilog, Linux, Git, PCIe, CXL
Model-written summary · the original posting is authoritative