Astera Labs
Design Engineering Intern (CCE2)
San Jose, CA, United States +1 · Internship · Posted Sep 7, 2026
- Location
- San Jose, CA, United States
California
About the job
Supports the CCE2 Design Engineering team in developing and validating RTL for advanced connectivity ASICs, from translating requirements into hardware behavior through simulation, debugging, and design-flow collaboration.
What you'll do
- Design, implement, modify, and document synthesizable RTL in Verilog or SystemVerilog.
- Run simulations and use waveforms, logs, assertions, and regression results to debug behavior and verify design changes.
- Collaborate with verification, physical design, DFT, firmware, validation, and architecture teams on design implementation and handoffs.
What they ask for
- Coursework, projects, research, or hands-on experience in electrical engineering, computer engineering, computer science, or a related field.
- Foundational understanding of digital logic, RTL, computer architecture, finite-state machines, computer arithmetic, or hardware interfaces.
- Experience with Verilog, SystemVerilog, VHDL, C/C++, Python, or another language used in digital design and automation.
- Comfort learning Linux and using command-line tools, source control, technical specifications, logs, waveforms, and development scripts.
Nice to have
- Experience with RTL design, simulation, assertions, lint, CDC/RDC, synthesis, formal analysis, or design-for-test concepts.
- Familiarity with connectivity technologies, EDA tools, scripting, or collaborative engineering workflows mentioned in the posting.
Pay
$35/hour to $55/hour (hourly rate); $500-per-week (housing/relocation stipend)
Tools
Verilog, SystemVerilog, VHDL, C/C++, Python, Linux, PCIe, CXL
Model-written summary · the original posting is authoritative