Astera Labs
Design Verification Engineer Intern
San Jose, CA +1 · Internship · Posted Sep 4, 2026
- Location
- San Jose, CA
California
About the job
Supports the Design Verification team in testing digital designs through simulation, regression, waveform analysis, coverage review, and collaboration with engineering teams.
What you'll do
- Develop or extend simulation tests and verification components, then run simulations and regressions.
- Analyze logs, assertions, simulation output, and waveforms to investigate failures and identify coverage gaps.
- Own and present an assigned verification project, collaborating with design, firmware, validation, and other teams.
What they ask for
- Coursework, projects, research, or hands-on experience in electrical engineering, computer engineering, computer science, or a related field.
- Foundational understanding of digital logic, computer architecture, RTL, hardware interfaces, or software development.
- Programming experience in one or more of SystemVerilog, Verilog, Python, C, C++, or a comparable language.
- Comfort learning in a Linux environment and working with source control, command-line tools, and technical documentation.
Nice to have
- Experience with SystemVerilog, UVM, constrained-random testing, assertions, scoreboards, monitors, drivers, or functional coverage.
- Experience with simulation and waveform-debug tools such as VCS, Verdi, or DVE.
Pay
$35/hour to $55/hour (base hourly pay); $500-per-week (housing/relocation stipend)
Tools
SystemVerilog, UVM, Python, Linux, VCS, Verdi, DVE, Git
Model-written summary · the original posting is authoritative