Astera Labs
Design Verification Tech Lead- SerDes/PHY IP
$160K–$200K
San Jose, California, United States +1 · Full-time · Posted Sep 21, 2026
- Location
- San Jose, California, United States
California - Experience
- 5+ years of design verification experience on high-speed SerDes, PHY, or mixed-signal IP.
- Education
- Bachelor's degree in Electrical Engineering, Computer Engineering, or related field.
About the job
Own functional verification of high-speed SerDes/PHY IP, from verification architecture and coverage closure through debugging and tape-out readiness.
What you'll do
- Architect UVM verification environments, plans, coverage models, and sign-off criteria for SerDes/PHY IP.
- Develop and execute testbenches and verify physical-layer behavior, protocols, and link scenarios; drive coverage closure and regressions.
- Set technical direction, mentor engineers, and collaborate with analog, SoC, firmware, validation, and customer teams.
What they ask for
- Bachelor's degree in Electrical Engineering, Computer Engineering, or related field.
- 5+ years of design verification experience on high-speed SerDes, PHY, or mixed-signal IP.
- Strong physical-layer knowledge and expert-level SystemVerilog and UVM proficiency.
- Hands-on analog/mixed-signal co-simulation and Real Number Modeling (RNM) experience; working knowledge of at least one listed high-speed serial protocol.
Nice to have
- MS or PhD in Electrical Engineering or Computer Engineering; experience with PCIe Gen 6/Gen 7, UALink, or UCIe SerDes/PHY IP.
- Emulation or gate-level simulation familiarity, Python or Perl scripting, post-silicon bring-up experience, or technical leadership across disciplines.
Pay
$160,000 to $200,000 USD base salary
Tools
SystemVerilog, UVM, Real Number Modeling (RNM), PCIe, UALink, UCIe, Ethernet, CXL
Model-written summary · the original posting is authoritative