Astera Labs
DFT Engineering Intern
San Jose, CA or Toronto, Ontario, Canada +1 · Internship · Posted Sep 4, 2026
- Location
- San Jose, CA or Toronto, Ontario, Canada
California
About the job
Supports the Design-for-Test team in implementing, verifying, and analyzing silicon test structures, patterns, and related DFT flows.
What you'll do
- Support DFT architecture, implementation, and flow activities such as scan insertion, memory test, and test-mode checks.
- Generate and analyze test patterns, simulations, coverage, reports, and failures to help debug DFT behavior.
- Develop or improve automation and collaborate with engineering teams to track and communicate issues.
What they ask for
- Coursework, projects, research, or hands-on experience in electrical engineering, computer engineering, computer science, or a related field.
- Foundational understanding of digital logic, RTL, computer architecture, semiconductor design, or hardware verification.
- Programming or scripting experience in one or more of Verilog, SystemVerilog, Python, Tcl, Perl, C, C++, or a comparable language.
- Comfort learning in Linux and using command-line tools, source control, and technical documentation.
Nice to have
- Experience with scan, ATPG, fault coverage, MBIST/BIST, boundary scan, JTAG, or manufacturing-test concepts.
- Experience with DFT/EDA tools, RTL or gate-level simulation, X-propagation, scripting, or high-speed connectivity technologies.
Pay
$35/hour to $55/hour (base salary); $500-per-week housing/relocation stipend
Tools
Verilog, SystemVerilog, Python, Tcl, Perl, C, C++, Linux
Model-written summary · the original posting is authoritative