Digital Design Engineering Intern

What you'll do

• Implement and review synthesizable Verilog or SystemVerilog RTL; translate block requirements into logic, state machines, datapaths, and interfaces.
• Create or improve simulations and checks, and run compile, elaboration, lint, CDC, and synthesis flows to identify issues.
• Collaborate across engineering teams and document design decisions, test results, and handoff information.

What they ask for

• Enrollment in a bachelor’s, master’s, or Ph.D. program in electrical engineering, computer engineering, computer science, or a related field.
• Coursework, research, or project experience in a relevant area such as digital logic, computer architecture, embedded systems, ASIC design, FPGA design, or hardware description languages.
• Programming or hardware-description-language experience with Verilog, SystemVerilog, VHDL, C, C++, Python, or a comparable language.
• Familiarity with digital design concepts and Linux development environments, Git, command-line tools, debugging, and technical documentation.

Nice to have

• Experience writing synthesizable RTL, simulation testbenches, SystemVerilog assertions, or reusable design IP.
• Exposure to lint, CDC, synthesis, formal verification, timing, or other design-quality checks; familiarity with VCS, SpyGlass, Design Compiler, PrimeTime, or comparable EDA tools.

Pay

$35/hour to $55/hour (hourly rate); $500-per-week (housing/relocation stipend)

Tools

Verilog, SystemVerilog, VHDL, C, C++, Python, Linux, Git