Astera Labs
Distinguished Formal Verification
$230K–$285K
San Jose, CA +1 · Principal · Full-time · Posted Feb 23, 2026
- Location
- San Jose, CA
California - Experience
- 15+ years in formal verification or 18+ years in traditional design verification with significant formal verification specialization.
- Education
- Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or related technical field.
About the job
Sets formal verification strategy and leads verification work across Astera Labs’ connectivity products, while mentoring engineers and supporting design quality.
What you'll do
- Define formal verification methodologies and best practices across product lines and advise engineering leadership on risk and design quality.
- Develop verification plans, models, abstractions, and assertions; use model checking and EDA tools to find corner-case bugs and achieve proof convergence.
- Mentor engineers, collaborate with design teams, and represent the company in industry forums and customer or executive presentations.
What they ask for
- Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related technical field.
- Strong proficiency in SystemVerilog/Verilog and deep understanding of hardware design verification.
- Advanced scripting abilities with Python or Perl.
- Ability to manage multiple high-impact tasks and collaborate across functions to influence technical direction.
Nice to have
- Master's or PhD in a related field focused on formal methods or verification.
- Experience with Synopsys VCFormal or Cadence JasperGold, bug hunting and static proof verification, CI/CD workflows, or relevant protocol standards bodies.
Pay
$230,000 to $285,000 USD base salary
Tools
SystemVerilog, Verilog, Python, Perl, Synopsys VCFormal, Cadence JasperGold, CI/CD, PCIe Gen 6/7
AI focus
Supports verification of connectivity products used in AI infrastructure; no direct AI development work is stated.
Model-written summary · the original posting is authoritative