Formal Verification and RTL Design Software Engineer

What you'll do

• Build LLM-powered assistants and multi-agent solutions for RTL checking and optimization, bug triage, formal verification, and report analysis.
• Integrate AI tools with existing CAD/EDA flows and maintain design databases and dashboards.
• Work with RTL design, DV, formal verification, and CAD/EDA teams to turn workflow needs into AI-assisted tools.

What they ask for

• Bachelor's or Master's degree in Electrical Engineering, Computer Science/Engineering, or equivalent experience.
• 4–10 years of industry software engineering experience with direct exposure to RTL design, static/lint verification, or formal verification.
• Proficiency in Python and strong fundamentals in data structures, algorithms, and software engineering practices.
• Experience with LLMs, including fine-tuning, multi-agent systems, RAG pipelines, and vector databases.

Nice to have

• Familiarity with Verilog/SystemVerilog and formal/static verification tools such as JasperGold or VC Formal.
• Experience applying AI/ML to EDA or CAD problems, or with version control, testing, CI/CD, formal properties, SVA, or static timing/lint tools.

Pay

USD 160,500 to USD 200,000 base salary

Tools

Python, LLMs, RAG, vector databases, Verilog, SystemVerilog, JasperGold, VC Formal

AI focus

Develops and deploys LLM-based applications, agents, assistants, and retrieval systems for RTL and physical design, verification, static analysis, and CAD/EDA workflows.