Astera Labs
Packaging Engineer Intern
San Jose, CA +1 · Internship · Posted Aug 27, 2026
- Location
- San Jose, CA
California - Education
- Working toward an M.S. or PhD in Electrical Engineering or a related field.
About the job
Supports semiconductor package design, simulation, documentation, and manufacturing readiness for connectivity products.
What you'll do
- Support package design, modeling, automation, and documentation, including SI/PI, thermal, and mechanical analyses.
- Organize package requirements and maintain design records; review layouts and support tape-out and manufacturing-readiness activities.
- Document and present analysis results, risks, and recommendations while collaborating with internal teams and suppliers.
What they ask for
- Working toward an M.S. or PhD in Electrical Engineering or a related field.
- Cumulative GPA of 3.3/4.0 or higher.
- Coursework in RF/microwave, communication systems and signal analysis, semiconductor manufacturing, or circuit design.
- Scripting or software-development experience in Python, Visual Basic, or equivalent programming languages.
Nice to have
- Experience with physical-design or layout tools such as AutoCAD, Cadence Allegro, Cadence APD/SiP, or comparable tools.
- Experience using 3D electromagnetic-simulation tools such as ANSYS Electronics Desktop, HFSS, HFSS 3D Layout, or SIwave.
Pay
$35/hour to $55/hour (hourly rate); $500-per-week (housing/relocation stipend)
Tools
Python, Visual Basic, AutoCAD, Cadence Allegro, Cadence APD/SiP, ANSYS Electronics Desktop, HFSS 3D Layout, Keysight ADS
Model-written summary · the original posting is authoritative