Astera Labs
Physical Design Engineer Intern
San Jose, CA, United States +1 · Internship · Posted Sep 7, 2026
- Location
- San Jose, CA, United States
California - Education
- Coursework, projects, research, or hands-on experience in electrical engineering, computer engineering, computer science, VLSI, or a related field.
About the job
Supports the physical-design team by taking an assigned digital-design block through RTL-to-signoff implementation, analyzing results, and helping improve design quality and flow infrastructure.
What you'll do
- Run an assigned block through physical-design stages from synthesis to signoff.
- Analyze timing, area, congestion, verification, and other quality-of-result reports; help investigate issues.
- Support PPA experiments and CAD/flow infrastructure improvements, documenting and presenting results.
What they ask for
- Coursework, projects, research, or hands-on experience in electrical engineering, computer engineering, computer science, VLSI, or a related field.
- Foundational understanding of digital logic, RTL, CMOS/ASIC design, computer architecture, timing, or semiconductor manufacturing.
- Experience with Linux, command-line tools, source control, or scripting through coursework, projects, research, or prior experience.
- Methodical debugging, ability to learn unfamiliar tools, communicate progress and blockers, and follow through on commitments.
Nice to have
- Experience in ASIC physical design, timing analysis, physical verification, EMIR, or related areas.
- Experience with scripting or EDA and reproducible-flow tools such as Tcl, Python, Bash, Fusion, Innovus, PrimeTime, Calibre, Voltus, Git, Bitbucket, P4, Slurm, or Snakemake.
Pay
$35/hour to $55/hour (hourly rate; base salary); $500-per-week (housing/relocation stipend)
Tools
Linux, Tcl, Python, Bash, Fusion, Innovus, PrimeTime, Calibre
Model-written summary · the original posting is authoritative