Astera Labs
Physical Design Engineer Intern (DM)
San Jose, CA, United States +1 · Internship · Posted Sep 7, 2026
- Location
- San Jose, CA, United States
California - Education
- Coursework, projects, research, or hands-on experience in electrical engineering, computer engineering, computer science, VLSI, or a related field.
About the job
Runs and evaluates an assigned digital-design block through physical implementation and signoff, while supporting flow improvements and PPA experiments.
What you'll do
- Run a block through the RTL-to-signoff flow and review timing, area, congestion, and signoff reports.
- Debug implementation or flow issues and conduct controlled PPA experiments, documenting results and tradeoffs.
- Contribute to CAD and flow infrastructure improvements and collaborate on design handoffs and signoff.
What they ask for
- Coursework, projects, research, or hands-on experience in electrical engineering, computer engineering, computer science, VLSI, or a related field.
- Foundational understanding of digital logic, RTL, CMOS/ASIC design, computer architecture, timing, or semiconductor manufacturing.
- Experience with Linux, command-line tools, source control, or scripting through coursework, projects, research, or prior experience.
- Methodical debugging, ability to learn unfamiliar tools, communicate progress and blockers, and follow through on commitments.
Nice to have
- Experience with ASIC physical design, timing analysis, physical verification, EMIR, or related implementation work.
- Experience with scripting or EDA and reproducible-flow tools such as Tcl, Python, Bash, Fusion Compiler, Innovus, PrimeTime, Calibre, or Voltus.
Pay
$35/hour to $55/hour (hourly rate); $500-per-week (housing/relocation stipend)
Tools
Fusion, Innovus, PrimeTime, Calibre, Voltus, Linux, Tcl, Python
Model-written summary · the original posting is authoritative