Astera Labs
Principal Design Verification Engineer- SerDes/PHY IP
$207K–$230K
San Jose, California, United States +1 · Principal · Full-time · Posted Oct 27, 2026
- Location
- San Jose, California, United States
California - Experience
- 8+ years of design verification experience on high-speed SerDes, PHY, or mixed-signal IP.
- Education
- Bachelor's degree in Electrical Engineering, Computer Engineering, or related field.
About the job
Own functional verification of high-speed SerDes/PHY IP, from verification architecture and coverage closure through debugging and tape-out sign-off.
What you'll do
- Architect UVM verification environments, plans, coverage models, and sign-off criteria for SerDes/PHY IP.
- Develop and run testbenches and regressions; verify link behavior and close coverage across functional, performance, and corner-case scenarios.
- Lead technical direction and collaborate with analog/mixed-signal, SoC, firmware, validation, and customer teams.
What they ask for
- Bachelor's degree in Electrical Engineering, Computer Engineering, or related field.
- 8+ years of design verification experience on high-speed SerDes, PHY, or mixed-signal IP.
- Expert-level proficiency in SystemVerilog and UVM; hands-on analog/mixed-signal co-simulation and Real Number Modeling (RNM) experience.
- Strong physical-layer knowledge and working knowledge of one or more of PCIe, UALink, UCIe, Ethernet, or CXL.
Nice to have
- MS or PhD in Electrical Engineering or Computer Engineering.
- Experience with PCIe Gen 6/Gen 7, UALink, or UCIe SerDes/PHY IP; emulation, gate-level simulation, scripting, or post-silicon bring-up experience.
Pay
USD 207,000 to USD 230,000 base salary
Tools
SystemVerilog, UVM, Real Number Modeling (RNM), PCIe, UALink, UCIe, Ethernet, CXL
AI focus
Verify SerDes/PHY connectivity IP used in rack-scale AI infrastructure.
Model-written summary · the original posting is authoritative