Principal Digital Design Engineer (AI Fabric)

What you'll do

• Define micro-architecture and develop complex digital blocks and subsystems; drive designs to production.
• Collaborate with verification, physical design, and DFT teams on coverage, debug, timing closure, and DFT implementation.
• Support silicon bring-up and debug, mentor junior engineers, and improve silicon development processes.

What they ask for

• Bachelor’s degree in electrical engineering or equivalent.
• 8+ years of hands-on experience developing complex SoC/silicon products in Server, Storage, and/or Networking markets.
• Experience with RTL design, timing closure, DFT, advanced CMOS nodes (≤7nm), and block ownership from architecture through GDS.
• Deep expertise in at least one high-speed protocol; proficiency with Cadence and/or Synopsys digital design flows; familiarity with UVM-based verification.

Nice to have

• Track record delivering multiple high-performance designs to production in data-center environments.
• Experience collaborating with embedded firmware teams, standard embedded processor subsystems, or design methodology/CAD automation.

Pay

$185,000.00 USD – $230,000.00 USD base salary

Tools

RTL, Cadence, Synopsys, UVM, PCIe, Ethernet, Infiniband, DDR

AI focus

Designs high-performance connectivity solutions that support AI infrastructure.