Drimva

Astera Labs

Principal Electrical Engineer – Smart Cable Modules

$185K–$240K

San Jose, California, United States +1 · Principal · Full-time · Posted Aug 27, 2026

Location
San Jose, California, United States
California
Experience
10-12+ years of progressive electrical engineering experience, with at least 5 years focused on high-speed SerDes-based interconnect, active copper cable, or optical/pluggable module products.
Education
Bachelor’s or Master’s degree in electrical engineering or closely related field.

About the job

Own the electrical architecture and lifecycle delivery of active copper smart cable modules and pluggable hardware for high-speed data center connectivity.

What you'll do

  • Define module electrical architecture and design standards, and lead technical reviews and design sign-off.
  • Drive schematic and PCB design, power delivery, management interfaces, and hardware validation and bring-up.
  • Lead cross-functional technical work with firmware teams, manufacturers, suppliers, and customers; mentor engineers and contribute to standards work.

What they ask for

  • Bachelor’s or Master’s degree in electrical engineering or a closely related field.
  • 10-12+ years of progressive electrical engineering experience, including at least 5 years focused on high-speed SerDes interconnect, active copper cable, or optical/pluggable module products.
  • Track record delivering production hardware with 56G / 112G and faster SerDes interfaces; expert signal-integrity knowledge and proficiency with Cadence Allegro / OrCAD.
  • Deep familiarity with OSFP, QSFP-DD800, and SFP-DD specifications; hands-on CMIS 5.x / SFF-8636 and I2C/MDIO experience; proven bring-up and debug experience.

Nice to have

  • Experience on 800G or beyond module programs, CPO or LPO architecture, or PCIe Gen 5/6 retimer designs.
  • Participation in standards bodies or Python scripting fluency for lab automation and hardware characterization.

Pay

USD 185,000 to USD 240,000 base salary

Tools

112G PAM4, 56G NRZ, Cadence Allegro, OrCAD, OSFP, QSFP-DD800, CMIS 5.x, SFF-8636

Model-written summary · the original posting is authoritative

First seen Oct 29, 2026 · Last verified Nov 5, 2026 (UTC)