Astera Labs
Principal Physical Design Engineer
$185K–$240K
San Jose, California, United States +1 · Principal · Full-time · Posted Mar 31, 2026
- Location
- San Jose, California, United States
California - Experience
- 8+ years; multiple tapeouts on advanced process nodes (7nm or below).
- Education
- Bachelor's degree in Electrical Engineering, Computer Engineering, or related field; MS preferred.
About the job
Own and lead physical implementation of high-performance connectivity SoCs from RTL through tapeout, driving PPA, timing, power, and signoff.
What you'll do
- Own RTL2GDS implementation, including synthesis, floorplanning, placement, CTS, routing, and signoff; lead tapeout and post-tapeout support.
- Drive timing, low-power, physical verification, and reliability closure across block- and chip-level designs.
- Develop physical design methodology and flows, mentor engineers, and partner with cross-functional teams on implementation decisions.
What they ask for
- Bachelor's degree in Electrical Engineering, Computer Engineering, or a related field.
- 8+ years of physical design experience, with multiple tapeouts on advanced process nodes (7nm or below).
- Expertise in synthesis, place & route, CTS, and timing closure using industry-standard tools.
- Proficiency in Tcl/Python scripting and a proven record delivering complex, high-frequency SoC designs to production.
Nice to have
- MS in Electrical Engineering or Computer Engineering.
- Experience with SerDes-heavy designs, PCIe Gen 6/7, UALink/UCIe SoCs, large hierarchical designs, or EMIR, thermal, and package co-design.
Pay
$185,000 to $240,000 USD base salary
Tools
Synopsys Fusion Compiler, ICC2, Cadence Innovus, PrimeTime, Tcl, Python, UPF, CPF
Model-written summary · the original posting is authoritative