Astera Labs
Principal Physical Design Engineer, STA
$209K–$250K
San Jose, California, United States +1 · Principal · Full-time · Posted May 20, 2026
- Location
- San Jose, California, United States
California - Experience
- ≥10 years.
- Education
- Bachelor’s in Electrical Engineering or Computer Science required; Master’s preferred.
About the job
Owns timing analysis and closure for connectivity ASICs, from RTL through sign-off, collaborating across design teams to achieve full-chip timing convergence.
What you'll do
- Drive timing closure, develop and validate SDC constraints, and manage I/O timing budgets across hierarchical designs.
- Run and improve multi-corner/multi-mode STA, analyze timing issues, and guide timing ECOs through closure.
- Partner with RTL, physical design, implementation, and verification teams on timing convergence and sign-off.
What they ask for
- Bachelor’s in Electrical Engineering or Computer Science.
- At least 10 years of timing analysis and sign-off experience for complex SoCs in Server, Storage, or Networking applications.
- Expertise in timing constraints, STA methodology, and block- and full-chip timing closure.
- Knowledge of advanced-node design flows and proficiency with Cadence and/or Synopsys toolchains; scripting ability in Tcl, Python, or Perl.
Nice to have
- Master’s degree; familiarity with high-speed SerDes or Ethernet PHY timing challenges.
- Knowledge of ECO methodologies, DFT tools, test coverage analysis, IP integration, or SystemVerilog/Verilog.
Pay
USD 209,000.00 USD – USD 250,000.00 (base salary)
Tools
TSMC 7nm, Cadence, Synopsys, Tcl, Python, Perl, SystemVerilog, Verilog
Model-written summary · the original posting is authoritative