Astera Labs
Principal/ Sr.Principal Digital Design Engineer
$185K–$230K
San Jose, California, United States +1 · Principal · Full-time · Posted Sep 14, 2026
- Location
- San Jose, California, United States
California - Experience
- 10+ years.
- Education
- Bachelor's degree in Electrical Engineering or equivalent.
About the job
Architects and implements complex digital designs for high-performance AI connectivity products, from micro-architecture through production and silicon bring-up.
What you'll do
- Define micro-architecture, implement RTL, and optimize power, performance, and area for complex digital blocks and subsystems.
- Lead timing closure, DFT implementation, IP integration, verification sign-off, and production delivery.
- Collaborate with verification and post-silicon teams, mentor engineers, and improve design methodologies and CAD automation.
What they ask for
- Bachelor's degree in Electrical Engineering or equivalent.
- 10+ years of hands-on experience developing complex SoC/silicon products in Server, Storage, and/or Networking markets.
- Expertise in architecture, micro-architecture, RTL coding, functional simulation, and synthesis; strong understanding of timing closure, GLS, and DFT.
- Deep expertise in at least one high-speed protocol and production experience with advanced CMOS nodes (≤7nm); proficiency with Cadence and/or Synopsys digital design flows.
Nice to have
- Master's degree in Electrical Engineering or related field; track record delivering multiple high-performance designs to production in data-center environments.
- Hands-on embedded firmware collaboration, familiarity with RISC-V or Arm subsystems, or contributions to design methodology, CAD automation, or design infrastructure.
Pay
$185,000 to $230,000 USD base salary
Tools
RTL, PCIe, CXL, Ethernet, DDR4/DDR5, Cadence, Synopsys, RISC-V
AI focus
Designs digital connectivity silicon supporting AI infrastructure.
Model-written summary · the original posting is authoritative