Drimva

Astera Labs

Product Technical Chip Lead, Senior Director

$260K–$295K

San Jose, California, United States +1 · Director · Full-time · Posted Apr 9, 2026

Location
San Jose, California, United States
California
Experience
15+ years.
Education
Bachelor's degree in Electrical Engineering, Computer Engineering, or related field.

About the job

Leads end-to-end technical execution and product lifecycle ownership for next-generation UALink switching chips, aligning engineering teams from architecture through tapeout, validation, and customer enablement.

What you'll do

  • Own product technical lifecycle, including architecture assumptions, design integration, validation strategy, readiness, and customer enablement.
  • Drive chip development from RTL to GDSII, including tapeout, signoff, and chip quality.
  • Align cross-functional teams, resolve risks and dependencies, and establish scalable processes and engineering practices.

What they ask for

  • Bachelor's degree in Electrical Engineering, Computer Engineering, or a related field.
  • 15+ years of experience across architecture, silicon design, validation, systems, or related domains.
  • Track record developing large-scale chips (300mm²+) through successful tapeout, with hands-on 2.5D/3D advanced packaging and chiplet architecture experience.
  • Strong understanding of RTL design, design verification, DFT, and physical design flows; experience with high-speed serial interfaces such as PCIe, Ethernet, or switching architectures.

Nice to have

  • Master's degree in Electrical Engineering or Computer Engineering.
  • Experience with UALink, UCIe, PCIe Gen5/Gen6/Gen7, Ethernet switching architectures, advanced process nodes, power management, clocking, high-speed analog integration, or fast-growing startups or hyperscale environments.

Pay

USD 260,000 to USD 295,000 base salary

Tools

UALink, UCIe, PCIe Gen6/Gen7, Ethernet, RTL, GDSII, DFT, 2.5D/3D advanced packaging

AI focus

Develops UALink switching products that support rack-scale AI and hyperscale data centers.

Model-written summary · the original posting is authoritative

First seen Oct 29, 2026 · Last verified Nov 6, 2026 (UTC)