Astera Labs
Senior Design Verification Engineer
$148K–$165K
San Jose, California, United States +1 · Senior · Full-time · Posted Oct 27, 2026
- Location
- San Jose, California, United States
California - Experience
- 2–5 years of experience in design verification for complex ASICs or SoCs.
- Education
- Bachelor’s degree in Electrical Engineering, Computer Engineering, or a related technical field; a Master’s degree in these fields is preferred.
About the job
Develops and drives verification of connectivity silicon, from verification planning and testbench development through coverage closure, debugging, and silicon readiness.
What you'll do
- Create verification plans, scenarios, coverage models, checkers, assertions, and scoreboards for block- and subsystem-level designs.
- Build and run reusable UVM-based SystemVerilog testbenches and regressions for PCIe, UALink, and UCI behavior.
- Analyze failures and coverage, close verification gaps, and collaborate on issue isolation and silicon bring-up readiness.
What they ask for
- Bachelor’s degree in Electrical Engineering, Computer Engineering, or a related technical field.
- Hands-on experience with SystemVerilog and UVM-based verification environments.
- Experience developing verification plans, testbenches, assertions, scoreboards, and functional coverage models.
- Familiarity with simulation, waveform-debug, regression, and coverage tools.
Nice to have
- Experience verifying PCIe, UALink, UCI, or other high-speed connectivity and switching protocols.
- Knowledge of protocol checkers, formal verification, emulation, or hardware acceleration methodologies; or Python, Perl, or Tcl for verification automation.
Pay
$148,500 to $165,000 (base salary)
Tools
SystemVerilog, UVM, PCIe Gen 6/Gen 7, UALink, UCI, Python, Perl, Tcl
Model-written summary · the original posting is authoritative