Astera Labs
Senior Design Verification Engineer
$148K–$165K
San Jose, California, United States +1 · Senior · Full-time · Posted Sep 28, 2026
- Location
- San Jose, California, United States
California - Experience
- 2–5 years of experience in design verification for complex ASICs or SoCs.
- Education
- Bachelor’s degree in Electrical Engineering, Computer Engineering, or a related technical field.
About the job
Develops and delivers verification for connectivity silicon, from test planning and testbench development through coverage closure, debugging, and silicon readiness.
What you'll do
- Develop block- and subsystem-level verification plans, scenarios, coverage models, checkers, assertions, and scoreboards.
- Build and maintain reusable UVM-based SystemVerilog testbenches and run simulations and regressions across connectivity protocols.
- Analyze coverage, debug failures, and collaborate with design and post-silicon teams on root-cause analysis and silicon readiness.
What they ask for
- Bachelor’s degree in Electrical Engineering, Computer Engineering, or a related technical field.
- 2–5 years of experience in design verification for complex ASICs or SoCs.
- Hands-on experience with SystemVerilog and UVM-based verification environments.
- Experience developing verification plans, testbenches, assertions, scoreboards, and functional coverage models.
Nice to have
- Experience verifying PCIe, UALink, UCI, or other high-speed connectivity and switching protocols.
- Knowledge of protocol checkers, formal verification, emulation, hardware acceleration, or verification automation using Python, Perl, or Tcl.
Pay
$148,500 to $165,000 (base salary)
Tools
SystemVerilog, UVM, PCIe Gen 6/Gen 7, UALink, UCI, Python, Perl, Tcl
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