Astera Labs
Senior Manager, Digital Design
$216K–$240K
San Jose, California, United States +1 · Manager · Full-time · Posted Sep 17, 2026
- Location
- San Jose, California, United States
California - Experience
- 3–5 years in engineering management or technical leadership in digital IC or ASIC design.
- Education
- Bachelor’s degree in Electrical Engineering, Computer Engineering, or a related technical field.
About the job
Leads digital design teams developing high-performance connectivity devices, from requirements and architecture through RTL, verification, tape-out, and shipment.
What you'll do
- Lead delivery of at least two complex devices, managing milestones, technical decisions, risks, and schedules.
- Establish RTL quality practices, design reviews, checklists, and signoff criteria; resolve design and integration issues with partner teams.
- Lead and develop 6–8 digital design engineers and align cross-functional teams on quality and execution.
What they ask for
- Experience in PCIe & CXL, UAL, or ethernet digital design, including protocol implementation and physical-layer considerations.
- Strong hands-on front-end RTL expertise and design practices that support physical design and tape-out quality.
- Ownership of at least two devices from requirements through tape-out and shipment.
- Ability to lead 6–8 engineers and influence cross-functional execution.
Nice to have
- Expertise in RTL quality methodologies, lint, clock-domain and reset-domain considerations, synthesis, timing, and signoff readiness.
- Experience improving design flows and tape-out processes; large physical floorplan blocks are a plus.
Pay
$216,000 to $240,000 USD base salary
Tools
PCIe, CXL, UAL, ethernet, RTL, ASIC, DFT
Model-written summary · the original posting is authoritative