Astera Labs
Senior Principal Digital Design Engineer
$205K–$255K
San Jose, CA +1 · Principal · Full-time · Posted Mar 12, 2026
- Location
- San Jose, CA
California - Experience
- 12+ years; no alternative stated.
- Education
- Bachelor's degree in Electrical Engineering or equivalent.
About the job
Leads architecture and RTL implementation of complex digital designs for AI connectivity silicon, from concept through production and silicon bring-up.
What you'll do
- Define micro-architecture and guide design decisions balancing performance, power, and area.
- Lead RTL execution, timing closure, DFT, and delivery of designs through GDS and silicon bring-up.
- Mentor engineers and collaborate with verification, physical design, DFT, post-silicon, firmware, and software teams.
What they ask for
- Bachelor's degree in Electrical Engineering or equivalent.
- 12+ years of hands-on experience developing complex SoC/silicon products in Server, Storage, and/or Networking markets.
- Expertise in architecture, micro-architecture, RTL coding, synthesis, and timing closure; deep knowledge of at least one high-speed protocol.
- Production experience with advanced CMOS nodes (≤7nm); proficiency with Cadence and/or Synopsys digital design flows; track record delivering multiple high-performance designs to production.
Nice to have
- Master's degree in Electrical Engineering or related field.
- Experience with multiple high-speed protocols, firmware collaboration, RISC-V or Arm subsystems, design methodology improvements, or technical team leadership.
Pay
$205,000 to $255,000 (base salary)
Tools
PCIe, CXL, UALink, Ethernet, DDR4/DDR5, Cadence, Synopsys, RISC-V
AI focus
Designs connectivity silicon supporting AI infrastructure; no direct AI model development is stated.
Model-written summary · the original posting is authoritative