Astera Labs
Signal Integrity Engineer Intern
San Jose, CA, United States +1 · Internship · Posted Sep 7, 2026
- Location
- San Jose, CA, United States
California - Experience
- No specific number of years stated.
- Education
- Enrollment in a bachelor’s, master’s, or Ph.D. program in electrical engineering, computer engineering, or a related field.
About the job
Supports the SI/PI team with simulation, measurement, and validation of high-speed interconnects in PCB and system designs.
What you'll do
- Perform pre-layout, layout, and post-layout signal-integrity analysis and help build simulation models.
- Assist with S-parameter extraction, lab measurements, and PCB/PCBA validation; organize and document results.
- Collaborate across engineering teams and contribute to technical reports, design reviews, and a final project presentation.
What they ask for
- Currently enrolled in a bachelor’s, master’s, or Ph.D. program in electrical engineering, computer engineering, or a related field.
- Academic, research, or project experience in at least one area such as high-speed digital design, signal integrity, transmission lines, electromagnetics, PCB design, differential signaling, or S-parameters.
- Foundational understanding of frequency-domain or time-domain analysis and how interconnect design affects signal quality.
- Ability to learn technical workflows, handle data carefully, communicate conclusions, and collaborate.
Nice to have
- Familiarity with PCB or system-level SI/PI simulation, channel analysis, or lab measurement.
- Exposure to high-speed analysis tools or workflows such as ADS, HFSS, CST, Keysight, Cadence, or equivalent; scripting or related analysis experience is also noted as preferred.
Pay
$35/hour to $55/hour (base hourly rate); $500-per-week (housing/relocation stipend)
Tools
ADS, HFSS, CST, Keysight, Cadence, Python, MATLAB, Touchstone/S-parameter files
Model-written summary · the original posting is authoritative