Astera Labs
Signal Integrity Solutions Architect Intern
San Jose, CA +1 · Internship · Posted Oct 22, 2026
- Location
- San Jose, CA
California - Experience
- No specific number of years stated.
- Education
- Currently pursuing a Bachelor's degree in Electrical Engineering, Computer Engineering, Physics, or a related technical field.
About the job
Models system-level signal-integrity channels for compute and switch architectures, assesses next-generation interconnect feasibility, and uses findings to inform product roadmaps and design choices.
What you'll do
- Build and evaluate channel models across compute and switch architectures and identify performance constraints.
- Analyze sensitivities and design trade-offs to determine channel performance drivers and margins.
- Present findings and collaborate with architecture, hardware, and silicon teams on signal-integrity goals and product roadmaps.
What they ask for
- Currently pursuing a Bachelor's degree in Electrical Engineering, Computer Engineering, Physics, or a related technical field.
- Coursework or project experience in signal integrity, transmission lines, electromagnetics, or high-speed digital design; basic understanding of high-speed serial link concepts.
- Familiarity with the physical layer of high-speed interconnect standards such as PCIe or Ethernet.
- Proficiency with a scripting or analysis tool such as Python or MATLAB.
Nice to have
- Currently pursuing a Master's or PhD in Electrical Engineering or a related field.
- Experience with channel simulation tools or S-parameter analysis, high-speed interconnects, or statistical/design-of-experiments methods.
Pay
$35/hour to $55/hour USD, hourly rate; $500-per-week USD housing/relocation stipend
Tools
PCIe, Ethernet, UALink, Python, MATLAB, Keysight ADS, Ansys HFSS, S-parameter
AI focus
Supports next-generation AI infrastructure by evaluating signal-integrity feasibility for system architectures and connectivity solutions.
Model-written summary · the original posting is authoritative