Astera Labs
STA Physical Design Engineer, Senior Principal
$205K–$260K
San Jose, California, United States +1 · Principal · Full-time · Posted Feb 23, 2026
- Location
- San Jose, California, United States
California - Experience
- ≥10 years.
- Education
- Bachelor’s in Electrical Engineering or Computer Science required; Master’s preferred.
About the job
Own physical design and timing signoff for connectivity ASICs, from RTL through GDS, collaborating with design and verification teams.
What you'll do
- Drive place-and-route activities and signoff for complex SoCs or subsystems.
- Identify RTL issues, refine constraints, and manage I/O timing budgets across hierarchical designs.
- Partner with design, implementation, and verification teams to achieve block and top-level convergence.
What they ask for
- Bachelor’s in Electrical Engineering or Computer Science.
- At least 10 years of PnR and sign-off experience for complex SoCs in Server, Storage, or Networking applications.
- Expertise in PnR, Extraction, Timing closure, EM-IR, Formality, and DRC/LVS; knowledge of advanced-node flows at 7nm or below.
- Proficiency with Cadence and/or Synopsys physical design/STA toolchains and scripting in Tcl, Python, or Perl.
Nice to have
- Master’s degree.
- Familiarity with high-speed SERDES and Ethernet PHY timing challenges; ECO methodologies, DFT tools, test coverage analysis, IP integration, or SystemVerilog/Verilog.
Pay
USD 205,000.00 USD – USD 260,000.00 base salary
Tools
Cadence, Synopsys, Tcl, Python, Perl, PT DMSA, SystemVerilog, Verilog
Model-written summary · the original posting is authoritative