Astera Labs
Synthesis & STA Engineer – High-Speed SerDes
$160K–$200K
San Jose, California, United States +1 · Full-time · Posted Oct 27, 2026
- Location
- San Jose, California, United States
California - Experience
- ≥8 years of experience in synthesis, timing constraints development, STA, and sign-off for high-speed mixed-signal IP in Server, Storage, Networking, or SerDes applications.
- Education
- Bachelor's in Electrical Engineering or Computer Science required; Master's preferred.
About the job
Own synthesis and static timing analysis for the digital portions of high-speed mixed-signal SerDes designs, driving timing closure from synthesis through sign-off.
What you'll do
- Optimize RTL synthesis for area, power, and timing; develop and validate SDC constraints and MMMC environments.
- Drive block- and chip-level timing closure, sign-off analysis, timing debug, and ECOs for SerDes designs.
- Build automation for STA runs and collaborate with analog, RTL, physical design, architecture, and verification teams.
What they ask for
- Bachelor's in Electrical Engineering or Computer Science.
- At least 8 years in synthesis, timing-constraint development, STA, and sign-off for high-speed mixed-signal IP in Server, Storage, Networking, or SerDes applications.
- Strong SDC and STA expertise, including timing closure using Synopsys PrimeTime and/or Cadence Tempus.
- Knowledge of advanced-node synthesis and implementation flows; proficiency with Cadence and/or Synopsys toolchains and scripting in Tcl, Python, or Perl.
Nice to have
- Master's degree.
- Experience with high-speed SerDes, Ethernet PHY (112G/224G), or PCIe/CXL PHY designs.
Pay
$160,000–$200,000 USD base salary
Tools
SDC, MMMC, TSMC 5nm/3nm, ETM/ILM, Synopsys PrimeTime, Cadence Tempus, Tcl, Python
Model-written summary · the original posting is authoritative