Astera Labs
Tech Lead, Digital Design Engineer
$176K–$195K
San Jose, California, United States +1 · Full-time · Posted Sep 30, 2026
- Location
- San Jose, California, United States
California - Experience
- 5–8 years.
- Education
- Bachelor’s degree in Electrical Engineering or a related field.
- Visa sponsorship
- Authorized to work in the United States.
About the job
Leads front-end digital design and block-level execution for high-performance switch ASICs, from microarchitecture and RTL through signoff and GDS delivery.
What you'll do
- Define microarchitecture, implement synthesizable RTL, and integrate reusable IP for switch ASIC blocks.
- Drive synthesis, timing closure, gate-level simulation, DFT, and GDS delivery; resolve performance, power, and area tradeoffs.
- Partner with verification and cross-functional teams on UVM-based debug, silicon bring-up, and technical execution.
What they ask for
- Bachelor’s degree in Electrical Engineering or a related field.
- 5–8 years developing or supporting complex SoC or silicon products for switch ASIC, networking, server, or storage applications.
- Hands-on experience with UALink, UCI, PCIe Gen 6/7, ESUN, and Ethernet.
- Front-end digital design experience spanning architecture, RTL, simulation, synthesis, timing closure, gate-level simulation, and DFT; block ownership through GDS using Synopsys and/or Cadence tools and flows. Authorized to work in the United States.
Nice to have
- Master’s degree in Electrical Engineering or a related field.
- PCIe or Ethernet switch experience; UVM verification, silicon bring-up/debug at 28nm or below, or Python or comparable scripting experience.
Pay
$175,500 to $195,000 USD base salary
Tools
UALink, UCI, PCIe Gen 6/7, ESUN, Ethernet, Synopsys, Cadence, UVM
AI focus
Designs switch ASIC connectivity technology for rack-scale AI infrastructure; no direct AI model development is stated.
Model-written summary · the original posting is authoritative