Astera Labs
Tech Lead Engineer, Design Verification
$176K–$195K
San Jose, California, United States +1 · Full-time · Posted Sep 28, 2026
- Location
- San Jose, California, United States
California - Experience
- 5–8 years of experience in design verification for complex ASICs or SoCs.
- Education
- Bachelor’s degree in Electrical Engineering, Computer Engineering, or a related technical field.
About the job
Leads design verification for connectivity silicon, developing verification strategies and testbenches, closing coverage, and supporting silicon readiness.
What you'll do
- Develop verification plans, scenarios, coverage models, checkers, assertions, and scoreboards for block- and subsystem-level features.
- Build and maintain reusable UVM-based SystemVerilog testbenches and run simulations and regressions across connectivity protocols.
- Drive coverage closure, debug issues, and collaborate with design and post-silicon teams on root-cause analysis and silicon readiness.
What they ask for
- Bachelor’s degree in Electrical Engineering, Computer Engineering, or a related technical field.
- 5–8 years of design verification experience for complex ASICs or SoCs.
- Hands-on experience with SystemVerilog and UVM-based verification environments.
- Experience developing verification plans, testbenches, assertions, scoreboards, and functional coverage models.
Nice to have
- Experience verifying PCIe, UALink, UCIe, or other high-speed connectivity and switching protocols.
- Knowledge of protocol checkers, formal verification, emulation, or hardware acceleration methodologies.
Pay
$175,500 to $195,000 USD base salary
Tools
SystemVerilog, UVM, PCIe Gen 6/Gen 7, UALink, UCIe, Python, PowerShell, Tcl
AI focus
Verifies connectivity silicon for rack-scale AI infrastructure, including products connecting AI accelerators, memory, and compute resources.
Model-written summary · the original posting is authoritative