Baidu USA
Design Verification Engineer
Sunnyvale,CA +1 · Full-time · Posted Jun 17, 2021
- Location
- Sunnyvale,CA
Sunnyvale, CA, United States - Experience
- Minimum 5 years of UVM-based verification on a significantly complex project.
About the job
Verify Baidu’s AI SoC functionality at block and SoC levels, from testbench development through coverage closure and bring-up debugging.
What you'll do
- Develop UVM testbenches, tests, reference and coverage models, and regression automation; perform RTL, gate-level, and mixed-signal verification.
- Analyze and debug failures, track bugs, and analyze and close coverage.
- Review specifications and architecture with design and systems teams, define verification plans, and support emulation and silicon bring-up debugging.
What they ask for
- Advanced knowledge of ASIC design and verification flows, simulation, SystemVerilog, and UVM.
- Solid verification skills, including constrained-random testing, coverage closure, gate-level simulation, and X propagation.
- Experience with one scripting language: Perl, Python, or Tcl; familiarity with C/C++.
- Excellent communication skills in both English and Chinese.
Nice to have
- SoC or IP verification experience in at least one of PCIe, Ethernet, HBM, GDDR, DDR, MMU, or Cache.
- Formal verification experience (model checking or equivalence checking).
Tools
UVM, System Verilog, Perl, Python, Tcl, C/C++, Verilog
AI focus
Verification of Baidu’s AI SoC and related AI silicon and system.
Model-written summary · the original posting is authoritative