Broadcom
Analog/Mixed Signal Verilog Modeling Design Engineer
USA-CA Irvine Alton Parkway Bldg 1 +1 · Full-time · Posted Jul 7, 2026
- Location
- USA-CA Irvine Alton Parkway Bldg 1
USA-CA San Jose Innovation Drive - Experience
- 8+ years of related experience.
- Education
- Bachelor's degree.
About the job
Develops SystemVerilog digital-mixed-signal models of analog IPs and supports their use in chip verification.
What you'll do
- Develop DMS models of analog IPs using SystemVerilog.
- Coordinate with analog design and chip DV teams to develop and support models for chip verification.
- Run SV-versus-schematic verification and create testbenches.
What they ask for
- Understand Verilog-AMS modeling.
- Have good knowledge of SystemVerilog UDT/UDR nettype, using Cadence wreal or EEnet package.
- Know analog circuits and digital RTL coding, including testbench creation.
- Have hands-on scripting skills in TCL, Perl, or Python.
Nice to have
- Familiarity with Cadence linting and simulation tools (ncsim, xrun, vcs) and analog schematic editor.
- Experience using AI tools such as Cursor or chipAgents to generate analog SV models and testbenches from a design spec.
Tools
SystemVerilog, Verilog-AMS, Cadence wreal, EEnet package, ncsim, xrun, vcs, TCL/Perl/Python
AI focus
Use AI tools such as Cursor and chipAgents to generate analog SV models and testbenches based on a design spec.
Model-written summary · the original posting is authoritative