Broadcom
ASIC Design Engineer
$122K–$195K
USA-CA Irvine Alton Parkway Bldg 2 +1 · Full-time · Posted Oct 13, 2026
- Location
- USA-CA Irvine Alton Parkway Bldg 2
USA-CA San Jose Innovation Drive - Experience
- BSEE and 8+ years of industry experience in high speed communication chip architecture and RTL design, or MSEE and 6+ years of industry experience.
- Education
- BSEE or MSEE.
About the job
Designs next-generation high-throughput Ethernet silicon, with a focus on PCIe and other host interfaces, as part of a worldwide design and architecture team.
What you'll do
- Contribute to front-end ASIC design, including architecture definition, RTL coding, simulation and verification, synthesis, timing closure, and silicon validation.
- Work with design and architecture teams to develop a new device.
- Contribute technical leadership opportunities.
What they ask for
- Hands-on ASIC design process experience, including architecture definition, RTL coding, simulation/verification, synthesis, timing closure, and silicon validation.
- Strong communication and documentation skills.
- Scripting skills using either Python/Perl.
- Self-starter and strong team player.
Nice to have
- Strong knowledge and background in either ethernet controller or PCIe.
Pay
USD 121,900.00 to USD 195,000.00 annual base salary
Tools
ASIC, RTL, Python, Perl, ethernet controller, PCIe
AI focus
Develops silicon technology for products serving AI and cloud data centers; no specific AI engineering work is stated.
Model-written summary · the original posting is authoritative