Broadcom
ASIC Design - Floorplan Engineer
USA-Colorado-Fort Collins-4380 Ziegler Road · Full-time · Posted Oct 30, 2026
- Experience
- 12+ years with a BS, or 10+ years with an MS.
- Education
- BS or MS in Electrical or Computer Engineering.
About the job
Defines and optimizes chip-level physical architecture and integration for advanced ASICs, from concept through production and tapeout.
What you'll do
- Define top-level floorplan architecture, including die sizing, hierarchy, and partitioning; drive macro placement, power grids, clock distribution, and pin placement.
- Lead top-level timing closure, congestion analysis, and ECO implementation; coordinate block-to-top-level integration and signoff.
- Support PPA optimization, design-flow automation, and methodology development for advanced process technologies.
What they ask for
- Strong foundation in VLSI design and ASIC physical design fundamentals, with in-depth floorplanning, die partitioning, and hierarchical design experience.
- Strong experience with TCL scripting and Linux environments.
- BS in Electrical or Computer Engineering with 12+ years of relevant experience, or MS in Electrical or Computer Engineering with 10+ years of relevant experience.
Nice to have
- Proficiency in Python, Perl, or Ruby.
- Experience with Cadence or equivalent physical design tools.
Tools
TCL, Linux, Python, Perl, Ruby, Cadence
AI focus
Physical architecture and integration for custom ASICs supporting AI products and SoCs; no direct AI model development is described.
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