Broadcom
ASIC Design Verification Engineer
$129K–$207K
USA-CA Irvine Alton Parkway Bldg 2 +2 · Full-time · Posted Jun 17, 2026
- Location
- USA-CA Irvine Alton Parkway Bldg 2
USA-MA-Andover-Brickstone Square-Suite 101
USA-CO Broomfield - Experience
- 12+ years of related experience with a bachelor’s degree, 10+ years with a master’s degree, or 3+ years with a PhD.
- Education
- Bachelor’s, master’s, or PhD degree; no equivalent-experience alternative stated.
About the job
Verifies high-throughput Ethernet silicon designs for cloud systems using constrained-random design verification methods.
What you'll do
- Verify new designs using industry-proven methodologies and drive completion through coverage closure.
- Work with worldwide design and architecture teams to develop products.
- Contribute to all aspects of design verification, with opportunities for technical leadership.
What they ask for
- Experience with constrained-random verification methodologies and driving completion via coverage closure.
- Strong teamwork and ability to work well with others.
Nice to have
- System Verilog and UVM; well versed in OOP.
- Scripting skills, such as Python or Perl.
Pay
$129,400.00 - $207,000.00 USD base salary
Tools
System Verilog, UVM, VCS, Incisive, Python, Perl, SVA
AI focus
The silicon products are described as accelerating AI/ML workflows; no AI development work is specified for this role.
Model-written summary · the original posting is authoritative