Broadcom
ASIC Design Verification Engineer
USA-CA Irvine Alton Parkway Bldg 2 +2 · Full-time · Posted Oct 15, 2026
- Location
- USA-CA Irvine Alton Parkway Bldg 2
USA-MA-Andover-Brickstone Square-Suite 101
USA-CO Broomfield - Experience
- 12+ years with a bachelor’s, 10+ years with a master’s, or 3+ years with a PhD.
- Education
- Bachelor’s, master’s, or PhD; no equivalent-experience alternative stated.
About the job
Verifies high-throughput Ethernet silicon designs for cloud systems using constrained-random verification methods, with a focus on coverage closure.
What you'll do
- Perform design verification across all aspects of the work.
- Use constrained-random methodologies to drive verification completion through coverage closure.
- Collaborate with worldwide design and architecture teams on new products.
What they ask for
- Experience with constrained-random verification methodologies and driving coverage closure.
- Bachelor’s degree and 12+ years of related experience, or a master’s degree and 10+ years, or a PhD and 3+ years.
Nice to have
- System Verilog and UVM skills; familiarity with object-oriented programming.
- Scripting skills, such as Python or Perl.
Tools
System Verilog, UVM, VCS, Incisive, Python, Perl
AI focus
The Ethernet devices being verified accelerate AI/ML workflows; no specific AI development work is stated.
Model-written summary · the original posting is authoritative