Broadcom
ASIC Implementation Engineer PD
$122K–$195K
USA-CA San Jose Innovation Drive · Full-time · Posted Sep 17, 2026
- Experience
- 8+ years with a Bachelor's degree, or 6+ years with a Master's degree.
- Education
- Bachelor's or Master's degree in Electrical Engineering.
About the job
Own top-level ASIC physical design from floorplanning through implementation, supporting next-generation AI and PCIe switch products through silicon tape-out.
What you'll do
- Own chip floorplanning, partition creation, and top-level clock tree and partition delivery.
- Resolve chip integration and assembly issues; coordinate floorplanning, I/O, and bump planning with the package team.
- Improve floorplan methodologies and evaluate vendors and IP against design specifications.
What they ask for
- Bachelor's degree in Electrical Engineering and 8+ years of relevant experience, or Master's degree in Electrical Engineering and 6+ years of relevant experience.
- Experience with top-level floorplanning focused on die-size estimation, partitioning, clocking, and pin planning.
- Experience resolving chip-level DRC/LVS/EMIR issues for advanced nodes and with bump planning, RDL implementation, and multi-voltage designs.
- Must work in person at the San Jose site; no remote work option.
Nice to have
- Experience with technologies such as Switch Fabric, Arbiter, High Speed DDR, SerDes, HBM, D2D I/O, or chiplets.
- Experience with hierarchical floorplanning, power-grid design, structured clocks, top-level pipeline planning, custom routes, scripting, and EDA tools.
Pay
USD 121,900.00 To USD 195,000.00 (annual base salary)
Tools
Python, Tcl, Perl, EDA tools
AI focus
Physical design work supporting next-generation Artificial Intelligence products.
Model-written summary · the original posting is authoritative