Broadcom
ASIC Package Design Engineer
$144K–$230K
USA-CA San Jose Innovation Drive +2 · Full-time · Posted Oct 19, 2026
- Location
- USA-CA San Jose Innovation Drive
USA-TX-Austin - River Place B7
USA-Colorado-Fort Collins-4380 Ziegler Road - Experience
- 12+ years with a BSEE or similar field, or 10+ years with an MSEE or similar field.
- Education
- BSEE or MSEE in a similar field.
About the job
Designs high-performance flip-chip BGA packages for ASICs, addressing physical layout, signal and power integrity, manufacturability, reliability, and thermal needs.
What you'll do
- Own ASIC package design, including critical structures for SerDes, ADC/DAC, DDR, and HBM.
- Coordinate work across multiple projects and manage project schedules and customer interfaces.
- Improve design-team efficiency through process development, automation, and documentation.
What they ask for
- BSEE or similar field and 12+ years’ experience in flip-chip-BGA package design, including high-speed SerDes, or MSEE or similar field and 10+ years’ work experience.
- Knowledge of package-level signal integrity and power integrity.
- Ability to collaborate with worldwide teams, including internal members and external vendor designers.
- Self-management and organization skills.
Nice to have
- Cadence APD (allegro package designer) or equivalent tool experience.
- 1 or more years experience with Cadence SKILL for Allegro, or similar design-automation coding experience and interest.
Pay
USD 143,800.00 To USD 230,000.00 (base salary)
Tools
Cadence APD, Cadence SKILL, SerDes, ADC/DAC, DDR, HBM
AI focus
Develops ASIC package designs for artificial intelligence (AI) applications.
Model-written summary · the original posting is authoritative