Broadcom
Design Engineer - STA
$110K–$176K
USA-Colorado-Fort Collins-4380 Ziegler Road · Full-time · Posted Sep 1, 2026
- Experience
- 8+ years with a BS, or 6+ years with an MS, in Electrical or Computer Engineering.
- Education
- BS or MS in Electrical or Computer Engineering.
About the job
Performs chip-level static timing analysis, architecture, and signoff closure for advanced ASIC and SoC designs.
What you'll do
- Develop and validate timing constraints and signoff methodologies across modes, corners, and design hierarchies.
- Analyze timing before and after routing, debug violations, evaluate results, and generate timing ECOs for closure.
- Automate timing flows and collaborate with physical design, synthesis, and clock teams to support timing convergence and power/performance optimization.
What they ask for
- Deep understanding of VLSI design principles and ASIC physical design fundamentals.
- Proficiency in creating, debugging, and validating timing constraints; knowledge of setup/hold, MMMC timing, and ECO convergence.
- Strong experience with Tcl scripting and Linux/UNIX environments.
- BS in Electrical or Computer Engineering with 8+ years of relevant experience, or MS in Electrical or Computer Engineering with 6+ years of relevant experience.
Nice to have
- Proficiency in Python, Perl, or Ruby.
- Hands-on experience with Synopsys and/or Cadence STA tools.
Pay
USD 109,700.00 To USD 175,500.00 annual base salary
Tools
Synopsys PrimeTime, Cadence Tempus, Tcl, Perl, Python, Ruby, Linux/UNIX, SPICE
AI focus
Supports timing analysis and closure for SoCs serving AI, computing, and networking products; no AI-specific development is stated.
Model-written summary · the original posting is authoritative