Broadcom
Design Engineer - STA
$129K–$207K
USA-Colorado-Fort Collins-4380 Ziegler Road · Full-time · Posted Aug 24, 2026
- Experience
- 12+ years with a BS, or 10+ years with an MS, in the specified fields.
- Education
- BS or MS degree in Electrical Engineering or Computer Engineering.
About the job
Performs static timing analysis (STA) for VLSI and ASIC designs, debugging timing issues and constraints and coordinating with engineering teams.
What you'll do
- Create and debug timing constraints; interpret timing-tool warnings, errors, and reports.
- Analyze setup, hold, signal integrity, crosstalk, and other timing checks; debug problems and develop solutions.
- Coordinate across engineering teams and organize and present technical data.
What they ask for
- Strong understanding of VLSI and ASIC physical design, basic PLLs and clock networks, and basic STA concepts.
- Experience using an STA tool; ability to create timing constraints and understand timing reports.
- TCL programming experience.
- BS in Electrical Engineering or Computer Engineering and 12+ years of related experience; or MS in either field and 10+ years of related experience.
Nice to have
- Synopsys PrimeTime and/or Cadence Tempus; experience with SPICE analysis.
- Experience in other coding languages; experience on timing SOIC/3DIC designs.
Pay
USD 129,400.00 to USD 207,000.00 annual base salary
Tools
Synopsys PrimeTime, Cadence Tempus, SPICE, TCL, Python, Ruby, BASH
Model-written summary · the original posting is authoritative