Broadcom
Design Engineer - Timing Methodology
$144K–$230K
USA-California-San Jose-1320 Ridder Park Drive · Full-time · Posted Aug 19, 2026
- Experience
- 12+ years of industry experience with a BS in EE/CS, or 10+ years with an MS or Ph.D. in EE/CS.
- Education
- BS degree in EE/CS, or MS degree or Ph.D. degree in EE/CS.
About the job
Develops and deploys timing sign-off methodologies and solutions for advanced-node SOC, 3D/2.5D IC, and multi-die designs.
What you'll do
- Develop and deploy timing sign-off methodologies for advanced technology nodes.
- Design and implement SOC, 3D/2.5D IC, and multi-die sign-off solutions.
- Participate in and lead EDA flow development for Primetime, Tempus, and Innovus.
What they ask for
- Hands-on experience in timing sign-off methodology development and ownership, SOC and 3D/2.5D IC timing sign-off, statistical data analysis and modeling, and silicon technologies, testability, and yield.
- Hands-on experience with industry-standard STA tools such as Primetime and Tempus.
- Hands-on experience developing scripts in TCL, Python, Perl, Unix shell, and flow automation.
- Experience with revision control, issue management/defect tracking, continuous integration, and continuous delivery/deployment tools.
Pay
USD 143,800.00 To USD 230,000.00 (base salary)
Tools
Primetime, Tempus, Innovus, TCL, Python, Perl, Unix shell
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