Broadcom
Design Implementation Engineer
$122K–$195K
USA-CA San Jose Innovation Drive +3 · Full-time · Posted Oct 19, 2026
- Location
- USA-CA San Jose Innovation Drive
USA-Allentown-1110 American Parkway NE
USA-Colorado-Fort Collins-4380 Ziegler Road
USA-CO Broomfield - Experience
- BS and 8+ years of related experience, or MS and 6+ years of related experience; at least 1–2 ASIC tapeouts in 7nm or lower technologies.
- Education
- BS or MS in Electrical Engineering, Computer Engineering, or related field.
About the job
Implements ASIC and SoC designs through place-and-route, timing closure, physical verification, and power optimization to meet performance, power, and area targets.
What you'll do
- Perform floor-planning, partitioning, placement, clock tree synthesis, routing, timing analysis and closure, and physical verification.
- Run equivalence checks and implement timing and functional ECOs; optimize power.
- Apply design methodologies and tools to achieve PPA targets and support tapeouts.
What they ask for
- Hands-on experience with timing analysis and place-and-route tools for ASIC/SoC design.
- Experience with design implementation at block and SoC level, including physical verification and/or constraints development and validation.
- Experience with formal verification, timing analysis, and ECO implementation.
- Tapeout of at least 1–2 ASICs in 7nm or lower technologies.
Nice to have
- Full-chip tapeout experience based on 7nm and lower technologies.
- Experience with Primetime, ICC2, Innovus, Caliber, LEC, or PrimeTime.
Pay
USD 121,900.00 To USD 195,000.00 annual base salary
Tools
Primetime, ICC2, Innovus, Caliber, LEC, PrimeTime
Model-written summary · the original posting is authoritative