Broadcom
Design Verification Engineer
$120K–$192K
USA-CA San Jose Innovation Drive · Full-time · Posted May 21, 2026
- Experience
- Typically: BS and 8+ years, MS and 6+ years, or PhD and 3+ years; equivalent accepted.
- Education
- BSEE, MSEE, or equivalent.
About the job
Verifies Broadcom networking switch and routing ASICs and subsystems, from test-plan development through pre-silicon coverage closure.
What you'll do
- Develop in-depth test plans for networking features, traffic management, scheduling, shaping, latency, and performance.
- Build verification environments, testbenches, APIs, and scripts, then implement test plans as executable test suites.
- Execute pre-silicon verification using functional and code coverage metrics.
What they ask for
- BSEE, MSEE, or equivalent, concentrated in digital design, with excellent academic standing.
- Familiarity with Verilog/SystemVerilog/UVM, Perl or Python, and object-oriented programming.
- Prior end-to-end ASIC/SOC verification experience, including test planning and coverage closure on silicon in mass production.
- Excellent verbal and written communication skills.
Nice to have
- Exposure to verification and validation methods using object-oriented, modular, reusable environments.
Pay
$120,000 - $192,000 USD base salary
Tools
Verilog, SystemVerilog, UVM, Perl, Python, Makefiles
AI focus
The ASICs support Scale-Out and Scale-Up AI Networks; the role verifies networking ASICs and does not specify AI development work.
Model-written summary · the original posting is authoritative