Broadcom
Design Verification Engineer
$144K–$230K
USA-CA San Jose Innovation Drive · Full-time · Posted Jun 19, 2026
- Experience
- 12+ years relevant industry experience preferred.
- Education
- Bachelor’s Degree in Electrical and Electronic Engineering, Computer Science, or equivalent.
- Visa sponsorship
- Must have legal authorization to work in the US.
About the job
Develops and verifies SoC and IP subsystems, building verification environments and tests, then debugging simulation failures and analyzing coverage.
What you'll do
- Develop verification environments, UVM agents, behavioral models, assertions, coverage, and directed and random tests.
- Verify designs at system and block levels against specifications.
- Debug simulation failures and analyze coverage results.
What they ask for
- Bachelor’s Degree in Electrical and Electronic Engineering, Computer Science, or equivalent.
- Experience verifying designs at system and block levels; strong experience in ASIC design verification flows and methodologies.
- Fluent knowledge of RTL verification methodologies, including System Verilog.
- Working knowledge of OVM, UVM, C/C++, Perl, and scripting; strong independent design-debugging capability.
Nice to have
- Experience with hardware design and debug, C++/SystemC, emulators, or FPGA-based prototyping.
- Familiarity with chip design methodologies and tools; knowledge of CPU, DDR, Bus Protocol, Network Protocol, or DSP design.
Pay
$143,800 - $230,000 USD base salary
Tools
System Verilog, UVM, OVM, C/C++, Perl, C++/SystemC
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