Broadcom
DFT Engineer
$122K–$195K
USA-CA San Jose Innovation Drive · Full-time · Posted Aug 31, 2026
- Experience
- Bachelor's Degree and 8+ years of related experience, or Master's Degree and 6+ years of related experience.
- Education
- Bachelor's Degree or Master's Degree
About the job
Supports DFT pattern bring-up and debug, yield improvement, failure analysis, and silicon evaluation for networking switch products.
What you'll do
- Generate, bring up, and debug ATPG and MBIST patterns; support post-silicon scan diagnostics and repair debug.
- Monitor wafer sort and final-test yield, analyze failures, and drive yield and cost improvements.
- Support new-product silicon bring-up and use AI tools to automate dashboards, wafer maps, and yield-correlation models.
What they ask for
- Deep understanding of CMOS device physics, semiconductor manufacturing processes, and electrical testing methodologies.
- Knowledge of SCAN, MBIST, bscan, scan-flow development, ATPG pattern generation, verification, and coverage analysis.
- Experience with Mentor/Siemens DFT Tessent for scan/MBIST/bscan/IJTAG pattern generation and debug.
- Post-silicon experience in pattern conversion for testers, pattern bring-up and debug, and silicon characterization.
Nice to have
- Strong scripting; experience with AI tools for quick script development is a plus.
Pay
USD 121,900.00 To USD 195,000.00 (base salary)
Tools
Mentor/Siemens DFT Tessent, ATPG, MBIST, SCAN, bscan, IJTAG
AI focus
Use AI tools to build automated dashboards, spatial wafer maps, and yield-correlation models; AI tools for quick script development are a plus.
Model-written summary · the original posting is authoritative